Title : | POWER & AREA EFFICIENT ROUTER IN 2-D MESH NETWORK-ON-CHIP USING LOW POWER METHODOLOGY - GATE LEVEL POWER OPTIMIZATION | |
Authors : | SUDHIR N. SHELKE & PRAMOD B. PATIL | |
Journal Title : | International Journal of Research in Computer Application and Management | |
Date : | 2012-12-16 | |
File : | Click to Download PDF |